huaqing/WMZ_1ST_STM32F103C8T6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

first upload

Browse Source
This commit is contained in:
huaqing
2026-02-24 00:22:53 +08:00
commit 7d84b7e1fa
925 changed files with 581335 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
MDK-ARM/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf Normal file
View File

@@ -0,0 +1,36 @@
// File: STM32F101_102_103_105_107.dbgconf
// Version: 1.0.0
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

36
MDK-ARM/RTE/Device/STM32F103C8/STM32F101_102_103_105_107.dbgconf.base@1.0.0 Normal file
View File

@@ -0,0 +1,36 @@
// File: STM32F101_102_103_105_107.dbgconf
// Version: 1.0.0
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <i> Reserved bits must be kept at reset value
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
// <o.2> DBG_STANDBY <i> Debug standby mode
// <o.1> DBG_STOP <i> Debug stop mode
// <o.0> DBG_SLEEP <i> Debug sleep mode
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

20
MDK-ARM/RTE/_WMZ_1ST_STM32F103C8T6/RTE_Components.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* UVISION generated file: DO NOT EDIT!
* Generated by: uVision version 5.43.1.0
*
* Project: 'WMZ_1ST_STM32F103C8T6'
* Target: 'WMZ_1ST_STM32F103C8T6'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

1932
MDK-ARM/WMZ_1ST_STM32F103C8T6.uvguix.hp Normal file
View File

File diff suppressed because one or more lines are too long

170
MDK-ARM/led.c Normal file
View File

@@ -0,0 +1,170 @@
#include "main.h"
#include "usart.h"
#include "gpio.h"
#include "oled.h"
#include "led.h"
void led(unsigned char color, unsigned char number)
{
unsigned char transfer[5];
transfer[0] = 2;
transfer[1] = 0;
if (number==1)
{
switch (color)
{
case 0:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); //B
showstring("1,0", 1 ,1);
break;
case 1:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); //B
showstring("1,1", 1 ,1);
break;
case 2:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); //B
showstring("1,2", 1 ,1);
break;
case 3:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET); //B
showstring("1,3", 1 ,1);
break;
case 4 :
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); //B
showstring("1,4", 1 ,1);
break;
case 5:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET); //B
showstring("1,5", 1 ,1);
break;
case 6:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET); //B
showstring("1,6", 1 ,1);
break;
case 7:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_RESET); //B
showstring("1,7", 1 ,1);
break;
default:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); //B
showstring("1,default", 1 ,1);
}
}
else if (number==2)
{
switch (color)
{
case 0:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET); //R
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 1:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); //R
transfer[0] = 2;
transfer[1] = 1;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 2:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET); //R
transfer[0] = 2;
transfer[1] = 2;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 3:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET); //R
transfer[0] = 2;
transfer[1] = 3;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 4 :
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); //R
transfer[0] = 2;
transfer[1] = 4;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 5:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); //R
transfer[0] = 2;
transfer[1] = 5;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 6:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET); //R
transfer[0] = 2;
transfer[1] = 6;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
case 7:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_RESET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_RESET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); //R
transfer[0] = 2;
transfer[1] = 7;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
break;
default:
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET); //R
transfer[0] = 2;
transfer[1] = 9;
HAL_UART_Transmit(&huart1,transfer, 2 ,1000);
}
}
else
{
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET); //R
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_5, GPIO_PIN_SET); //B
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); //G
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET); //R
}
transfer[0] = 2;
transfer[1] = 0;
}

1
MDK-ARM/led.h Normal file
View File

@@ -0,0 +1 @@
void led(unsigned char color, unsigned char number);

305
MDK-ARM/startup_stm32f103xb.s Normal file
View File

@@ -0,0 +1,305 @@
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END